This invention relates in general to memory writing and, more specifically, to an apparatus and methods for allowing burst writes to memory.
Performance of computer systems is heavily dependent upon memory architecture. Processors which are clocked at ever increasing frequencies suffer from bottlenecks when data is passed to dynamic random access memory (DRAM) which is external to the processor. Today, microprocessors are being clocked at frequencies upward of one gigahertz while DRAM memory is commonly clocked at frequencies less than two hundred megahertz. Memory is still evolving to operate at faster frequencies, but still memory lags behind the frequencies of microprocessors.
Because the external memory operates at a frequency much lower than the frequency of the processor, the processor occasionally must wait for a write operation to complete before issuing new instructions. For example, a number of writes to external memory could stall the processor if the processor operates at a frequency of one gigahertz and the memory runs at two hundred megahertz because five write operations can be issued by the processor for each memory cycle. As those skilled in the art appreciate, stalling the processor is undesirable.
Memory is written in discrete data packets. Each data packet is preceded by an address for that data packet. For each write to memory, a number of processor clock cycles are required to write each data packet. For example, in order to write four words of data, the sequence includes writing the following to the memory bus: a first address, a first word, a second address, a second word, a third address, a third word, a fourth address and a fourth word. The address cycle can take three processor clock cycles while the data cycle can take only one cycle. Transferring the above four words takes a total of sixteen clock cycles.
To increase memory bandwidth, different varieties of memory have been developed. These variants include page mode DRAM, synchronous DRAM and double data rate DRAM. These new memory variants allow bursting data to them in a way which increases data bandwidth to the memory. Bursting involves writing the address to memory once and following the address with a number of data packets. For example, to write a block of four words of data, the sequence includes writing a single address followed by the four words in succession to the memory bus. This approach presumes the block of four words are related to a single address, for example, the four words could be in adjacent memory locations. Using the same timing as the non-burst example in the preceding paragraph, the four words are transferred in seven clock cycles.
Although bursting can improve the bandwidth to memory, processing systems under-utilize this feature. A large proportion of writes to memory are single words. These single words cannot take advantage of the bursting feature in memory. Accordingly, techniques and hardware for better utilizing the burst mode of memory are desired.
According to the invention, disclosed are an apparatus and methods for buffering write operations. In one embodiment, a processing system is disclosed which bursts data to a bus. The processing system includes a memory cache, a write buffer unit, and a control unit. The memory cache produces an address and data. Included in the write buffer unit are a plurality of data locations coupled to the memory cache. The control unit directs the first data to any of the plurality of data locations.
In another embodiment, a method for optimizing storage in a write buffer unit is disclosed. First data and a first address are received. The first data is stored in the write buffer unit. Second data and a second address are also received. A determination is made whether the second address and the first address correspond to the same data block. The second data is stored in the write buffer unit.
In yet another embodiment, a method for storing data in a write buffer unit and dispensing those data to a bus is disclosed. In a first step, a plurality of data and a plurality of addresses respectively associated therewith are received. The plurality of data is arranged in the write buffer unit according to the plurality of addresses respectively associated therewith. A data block associated with a block address is burst to the bus.